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(parent: 39bc59c) | patch
hdl.ir: when adding sync domain to a design, also add it to ports.
authorwhitequark <whitequark@whitequark.org>
Wed, 15 May 2019 06:44:50 +0000 (06:44 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 15 May 2019 06:44:50 +0000 (06:44 +0000)
commitc337246fc581ccac0273f5661f65815266144862
treedb90005d694322c340589d008f0f3f192e4a0c4dtree
parent39bc59c924c39b8e813c392a36e41fb279a9b1d2commit | diff
hdl.ir: when adding sync domain to a design, also add it to ports.

Otherwise we end up in a situation where the examples don't have
clk and rst as ports, which is not nice.

Fixes #67.
nmigen/hdl/ir.py diff | blob | history
nmigen/test/test_hdl_ir.py diff | blob | history