build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 1 May 2018 10:02:54 +0000 (12:02 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 1 May 2018 10:02:54 +0000 (12:02 +0200)
commitc3652935d9f0560ac32d55335b56a11199c45878
tree490f61ac29748dbe1e4b38db3d8dfb5400852e73
parent121eaba722e0b0b732003473630362dba4d48182
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
litex/build/generic_platform.py
litex/build/lattice/diamond.py
litex/gen/fhdl/verilog.py