Merge with the main repo.
authorGabe Black <gblack@eecs.umich.edu>
Sat, 28 Jan 2012 15:24:01 +0000 (07:24 -0800)
committerGabe Black <gblack@eecs.umich.edu>
Sat, 28 Jan 2012 15:24:01 +0000 (07:24 -0800)
commitc3d41a2def15cdaf2ac3984315f452dacc6a0884
tree5324ebec3add54b934a841eee901983ac3463a7f
parentda2a4acc26ba264c3c4a12495776fd6a1c4fb133
parent4acca8a0536d4445ed25b67edf571ae460446ab9
Merge with the main repo.

--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
70 files changed:
src/arch/alpha/linux/system.cc
src/arch/alpha/linux/system.hh
src/arch/alpha/remote_gdb.cc
src/arch/alpha/system.cc
src/arch/alpha/system.hh
src/arch/alpha/utility.cc
src/arch/arm/utility.cc
src/arch/mips/linux/system.cc
src/arch/mips/stacktrace.cc
src/arch/mips/system.cc
src/arch/mips/utility.cc
src/arch/mips/vtophys.cc
src/arch/sparc/utility.cc
src/arch/x86/interrupts.cc
src/arch/x86/interrupts.hh
src/base/remote_gdb.cc
src/cpu/BaseCPU.py
src/cpu/base.cc
src/cpu/base.hh
src/cpu/checker/thread_context.hh
src/cpu/inorder/cpu.cc
src/cpu/inorder/cpu.hh
src/cpu/inorder/resources/cache_unit.cc
src/cpu/inorder/resources/cache_unit.hh
src/cpu/inorder/thread_context.cc
src/cpu/inorder/thread_context.hh
src/cpu/o3/O3CPU.py
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/fetch_impl.hh
src/cpu/o3/iew.hh
src/cpu/o3/lsq.hh
src/cpu/o3/thread_context.hh
src/cpu/o3/thread_context_impl.hh
src/cpu/ozone/cpu.hh
src/cpu/ozone/cpu_impl.hh
src/cpu/ozone/front_end_impl.hh
src/cpu/ozone/lw_lsq.hh
src/cpu/simple/atomic.cc
src/cpu/simple/timing.cc
src/cpu/simple_thread.cc
src/cpu/simple_thread.hh
src/cpu/thread_context.hh
src/cpu/thread_state.cc
src/cpu/thread_state.hh
src/dev/Device.py
src/dev/Pci.py
src/dev/arm/RealView.py
src/dev/arm/gic.cc
src/dev/arm/gic.hh
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/pcidev.cc
src/dev/pcidev.hh
src/dev/sparc/iob.cc
src/dev/x86/i82094aa.hh
src/kern/tru64/tru64.hh
src/mem/SConscript
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/physical.cc
src/mem/se_translating_port_proxy.cc
src/sim/System.py
src/sim/process.cc
src/sim/process.hh
src/sim/process_impl.hh
src/sim/syscall_emul.hh
src/sim/system.cc
src/sim/system.hh
tests/configs/simple-timing-ruby.py