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(parent: f425d9e) | patch
radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 8 Nov 2018 10:16:45 +0000 (11:16 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 8 Nov 2018 10:20:03 +0000 (11:20 +0100)
commitc472ad82e48e139e03ed28a7a98481814260d08e
tree78b80276779761af28d71efd4a1996414c602b49tree
parentf425d9ee74ce81be3aa9dfefad572d40c5d42372commit | diff
radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK

HTILE is supported on these chips, not sure how I missed that.
This restores using PFP_SYNC_ME when LOAD_CONTEXT_REG is not used.

Fixes: f425d9ee74 ("radv: use LOAD_CONTEXT_REG when loading fast clear values")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
src/amd/vulkan/radv_cmd_buffer.c diff | blob | history