mem: Add DDR3 and LPDDR2 DRAM controller configurations
authorAndreas Hansson <andreas.hansson@arm.com>
Thu, 31 Jan 2013 12:49:14 +0000 (07:49 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Thu, 31 Jan 2013 12:49:14 +0000 (07:49 -0500)
commitc4898b15bcf5458e35f17cb0c3b4185cec0081aa
tree7c95a64cb04c3824fa4e2ac514f52fb92be1f58d
parenteaa37e611f07a41d97a078bf2588bfe745d83751
mem: Add DDR3 and LPDDR2 DRAM controller configurations

This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
configs/common/FSConfig.py
src/mem/SimpleDRAM.py
tests/configs/inorder-timing.py
tests/configs/o3-timing-checker.py
tests/configs/o3-timing-mp.py
tests/configs/o3-timing.py
tests/configs/tgen-simple-dram.py