arch-arm,cpu: Add initial support for Arm SVE
authorGiacomo Gabrielli <giacomo.gabrielli@arm.com>
Tue, 16 Oct 2018 15:09:02 +0000 (16:09 +0100)
committerGiacomo Gabrielli <giacomo.gabrielli@arm.com>
Thu, 14 Mar 2019 10:42:27 +0000 (10:42 +0000)
commitc4cc3145cd1eeed236b5cd3f7b2424bc0761878e
treeb38eab6f5f389dfc53c2cf74275a83bacd2e9b18
parent91195ae7f637d1d4879cc3bf0860147333846e75
arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
46 files changed:
src/arch/arm/ArmISA.py
src/arch/arm/ArmSystem.py
src/arch/arm/SConscript
src/arch/arm/decoder.cc
src/arch/arm/decoder.hh
src/arch/arm/insts/static_inst.cc
src/arch/arm/insts/static_inst.hh
src/arch/arm/insts/sve.cc [new file with mode: 0644]
src/arch/arm/insts/sve.hh [new file with mode: 0644]
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/arm/isa/formats/aarch64.isa
src/arch/arm/isa/formats/formats.isa
src/arch/arm/isa/formats/sve_2nd_level.isa [new file with mode: 0644]
src/arch/arm/isa/formats/sve_top_level.isa [new file with mode: 0644]
src/arch/arm/isa/includes.isa
src/arch/arm/isa/insts/fp64.isa
src/arch/arm/isa/insts/insts.isa
src/arch/arm/isa/insts/ldr64.isa
src/arch/arm/isa/insts/mem.isa
src/arch/arm/isa/insts/neon64.isa
src/arch/arm/isa/insts/neon64_mem.isa
src/arch/arm/isa/insts/sve.isa [new file with mode: 0644]
src/arch/arm/isa/operands.isa
src/arch/arm/isa/templates/sve.isa [new file with mode: 0644]
src/arch/arm/isa/templates/templates.isa
src/arch/arm/miscregs.cc
src/arch/arm/miscregs.hh
src/arch/arm/miscregs_types.hh
src/arch/arm/nativetrace.cc
src/arch/arm/process.cc
src/arch/arm/registers.hh
src/arch/arm/system.cc
src/arch/arm/system.hh
src/arch/arm/types.hh
src/arch/arm/utility.cc
src/arch/arm/utility.hh
src/arch/generic/vec_reg.hh
src/cpu/FuncUnit.py
src/cpu/exetrace.cc
src/cpu/minor/MinorCPU.py
src/cpu/o3/FUPool.py
src/cpu/o3/FuncUnitConfig.py
src/cpu/op_class.hh
src/cpu/simple_thread.cc
util/cpt_upgraders/arm-sve.py [new file with mode: 0644]