gen/fhdl/verilog: set direction to io signals
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 29 Oct 2018 10:41:04 +0000 (11:41 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 29 Oct 2018 10:41:04 +0000 (11:41 +0100)
commitc506c9752cc575936c5cfadcabd5729459d8f3da
treea1919b10396ba61cce2baa8b0a857b2ebf73a322
parent49dab3b448b7f20398774a199272b7b4708f544e
gen/fhdl/verilog: set direction to io signals
litex/gen/fhdl/verilog.py