i965/sync: Implement DRI2_Fence extension
authorChad Versace <chad.versace@intel.com>
Wed, 6 May 2015 02:05:32 +0000 (19:05 -0700)
committerChad Versace <chad.versace@intel.com>
Thu, 7 May 2015 15:11:22 +0000 (08:11 -0700)
commitc636284ee8ee95bb3f3ad31aaf26a9512ec5006c
tree5c8fb49d221d1f82d065b523dfef0e61dc3b5c26
parent2516d835b17563b097efa3a980c3b9b5e77d7f00
i965/sync: Implement DRI2_Fence extension

This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync.

Below is the difference in piglit results, before and after this patch.
No regressions and several tests improve from 'skip' to 'pass'. Out of
EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other
tests pass.

  cmdline: piglit run -p gbm -t sync tests/quick.py
  mesa: master@1ac7db0
  piglit: 4069bec
  hw: Ivybridge

        | before after
  ------+-------------
   pass |     32    46
   fail |      0     0
  crash |      0     0
   skip |     35    21
  total |     67    67

v2:
  - Set fence->signalled = true in brw_fence_has_completed() too.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
docs/relnotes/10.6.0.html
src/mesa/drivers/dri/i965/intel_screen.c
src/mesa/drivers/dri/i965/intel_screen.h
src/mesa/drivers/dri/i965/intel_syncobj.c