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(parent: d88a7c1) | patch
add implementation of CSR SV CFG regs 0-7
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Sep 2018 04:49:13 +0000 (05:49 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 29 Sep 2018 04:49:13 +0000 (05:49 +0100)
commitc6d6d407fcf54d65290dab68578265d55ce70b1f
treea4dbe2a351c647d39ea6254722fbe63d9f31b91etree
parentd88a7c1700397abab309250bdbb8ceadb1cbc249commit | diff
add implementation of CSR SV CFG regs 0-7

this is a CAM table of key-value entries, 5-bits key (from instruction)
6-bits value (actual register table, now 64 entries)

TODO: obviously RV32E that would be reduced.
TODO: make it optional to have 32-32
riscv/processor.cc diff | blob | history
Simple-V augmented version of spike