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(parent: d96ee21) | patch
Make wishbone_master_out and wb_io_master_out match
authorAnton Blanchard <anton@linux.ibm.com>
Sun, 20 Dec 2020 10:11:17 +0000 (21:11 +1100)
committerAnton Blanchard <anton@ozlabs.org>
Sun, 20 Dec 2020 10:11:17 +0000 (21:11 +1100)
commitc6dfc19d890bcf79f59cb8e68e23a50214ef1b60
treeb01b3adf3aefcab8e449f8cfb1d7c620f7e33780tree
parentd96ee21c39f49390b8495dbde3172d86b666c2f3commit | diff
Make wishbone_master_out and wb_io_master_out match

This makes it easier to parse the records in verilog because they
are getting flattened into an array of bits by ghdl/yosys.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
wishbone_types.vhdl diff | blob | history