divider: Add an output register

divider: Add an output register

This puts the output of the divider through a register.  With the
addition of the logic to detect overflow, the combinatorial output
logic of the divider was becoming a critical path.  Adding the
output register adds a cycle to the latency of the divider but
helps make timing at 100MHz on the A7-100.

This also makes the valid, write_reg_enable and write_cr_enable
fields of the output be registered, which eliminates warnings
about register/latch pins with no clock.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>