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(parent: dc4a0aa) | patch
mem: Make LL/SC locks fine grained
authorMitch Hayenga <mitch.hayenga+gem5@gmail.com>
Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)
committerMitch Hayenga <mitch.hayenga+gem5@gmail.com>
Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)
commitc7dbd5e7686bbb065dfe2a74b92f4d9463ddfa80
treec7032e991c9e5d15e1d06f4695be9538e33ba3detree
parentdc4a0aa2fa1bc3767785b552159ab0ebe5baa72ecommit | diff
mem: Make LL/SC locks fine grained

The current implementation in gem5 just keeps a list of locks per cacheline.
Due to this, a store to a non-overlapping portion of the cacheline can cause an
LL/SC pair to fail.  This patch simply adds an address range to the lock
structure, so that the lock is only invalidated if the store overlaps the lock
range.
src/mem/cache/blk.hh diff | blob | history