arch: Introduce a base class for ISA classes.
authorGabe Black <gabeblack@google.com>
Tue, 4 Feb 2020 00:06:38 +0000 (16:06 -0800)
committerGabe Black <gabeblack@google.com>
Wed, 5 Feb 2020 22:41:47 +0000 (22:41 +0000)
commitc8079dd745d0b1632e8d7b9befa4f293e6fbe3f5
treeb4e8542bc6175d9fd6966435cfd73bd86b7e146d
parentc8a102c6afcdf0c71b3706f81030195e57f84203
arch: Introduce a base class for ISA classes.

These don't have anything in them at the moment since making some ISA
methods virtual and not inlined will likely add overhead, specifically
the ones for flattening registers. Some code may need to be rearranged
to minimize that overhead before the ISA objects can be truly put
behind a generic interface.

Change-Id: Ie36a771e977535a7996fdff701ce202bb95c8c58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
24 files changed:
src/arch/alpha/AlphaISA.py
src/arch/alpha/isa.cc
src/arch/alpha/isa.hh
src/arch/arm/ArmISA.py
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/generic/BaseISA.py [new file with mode: 0644]
src/arch/generic/SConscript
src/arch/generic/isa.hh [new file with mode: 0644]
src/arch/mips/MipsISA.py
src/arch/mips/isa.cc
src/arch/mips/isa.hh
src/arch/power/PowerISA.py
src/arch/power/isa.cc
src/arch/power/isa.hh
src/arch/riscv/RiscvISA.py
src/arch/riscv/isa.cc
src/arch/riscv/isa.hh
src/arch/sparc/SparcISA.py
src/arch/sparc/isa.cc
src/arch/sparc/isa.hh
src/arch/x86/X86ISA.py
src/arch/x86/isa.cc
src/arch/x86/isa.hh