Define clock domains instead of passing extra clocks as regular signals
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 10 Sep 2012 22:21:07 +0000 (00:21 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 10 Sep 2012 22:21:07 +0000 (00:21 +0200)
commitc86dd3cbefcc282ad59c40dd81c78edcf81f56f5
tree729ef3bdd9c9883fc5fb552e0cffc98b0c0c1b32
parent5931c5eb592d81b7dc68ab1d43e2114dadea83cb
Define clock domains instead of passing extra clocks as regular signals
constraints.py
milkymist/framebuffer/__init__.py
milkymist/m1crg/__init__.py
milkymist/s6ddrphy/__init__.py
top.py
verilog/m1crg/m1crg.v