Make _PySignalState CRTL-aware
authorMikolaj Wielgus <wielgusmikolaj@gmail.com>
Wed, 22 Dec 2021 14:22:16 +0000 (14:22 +0000)
committerMikolaj Wielgus <wielgusmikolaj@gmail.com>
Wed, 22 Dec 2021 14:24:09 +0000 (14:24 +0000)
commitc92be5de9c10a78a5cc3efef928b6843ece916f6
tree98de8f9e9f7b3479f59159ea21565b23d25374a9
parent768b9e05c96d9aede624f2c79af3409cc7cf7571
Make _PySignalState CRTL-aware
src/openpower/decoder/test/_pyrtl.py
src/openpower/decoder/test/pysim.py