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(parent: da5c997) | patch
fix fcvttg FPSCR.FR computation
authorJacob Lifshay <programmerjake@gmail.com>
Fri, 19 May 2023 03:53:23 +0000 (20:53 -0700)
committerJacob Lifshay <programmerjake@gmail.com>
Fri, 19 May 2023 03:53:23 +0000 (20:53 -0700)
commitc92e1804d74b4366421839f8f7b357f2753910a7
treec463dbea660bc0306b4f78e1ce377b7b92b27786tree
parentda5c99707775d50154a21076613393b694dca056commit | diff
fix fcvttg FPSCR.FR computation

the unit test previously assumed the rounding mode is truncate,
but when I switched it to allow dynamic rounding modes,
I forgot to no longer hard-code FPSCR.FR = 0
openpower/isa/fpcvt.mdwn diff | blob | history
src/openpower/test/fmv_fcvt/fmv_fcvt.py diff | blob | history