RISC-V: Compress 3-operand beq/bne against x0.

RISC-V: Compress 3-operand beq/bne against x0.

This lets us accept an instruction like
	beq a2,x0,.Label
and generate a compressed beqz.  This will allow some future simplications
to the gcc support, e.g. eliminating some duplicate patterns, and avoiding
adding new duplicate patterns, since currently we have to handle signed
and equality compares against zero specially.

Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils
and gcc.  There were no regressions.

	gas/
	* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
	(riscv_ip) <'C'>: Add 'z' support.
	opcodes/
	* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
	<bne>: Likewise.