Improved verilog output for ordinary $mux cells
authorClifford Wolf <clifford@clifford.at>
Sat, 2 Aug 2014 19:10:08 +0000 (21:10 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 2 Aug 2014 19:10:08 +0000 (21:10 +0200)
commitca1b5d50e0e577a88ae265b71679b81e71980db8
treea030da8ad8fa3aa92dbffee81a7f6e6e76d67636
parentb6acbc82e6a2954d453188a9997da2a30731ddac
Improved verilog output for ordinary $mux cells
backends/verilog/verilog_backend.cc