add misaligned mem test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:26:45 +0000 (13:26 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:16 +0000 (19:51 +0100)
commitca28f79c5ffc6ed26cf732d993b9a296fa8cf108
treede003ed8134983b4269daf4c348260cb7d797699
parentd9ad6b728bbc46efd4846d0670e8ae126381bc7a
add misaligned mem test
src/openpower/decoder/isa/mem.py
src/openpower/decoder/isa/test_mem.py