Make wishbone addresses be in units of doublewords or words
authorPaul Mackerras <paulus@ozlabs.org>
Wed, 15 Sep 2021 08:18:09 +0000 (18:18 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Wed, 15 Sep 2021 08:18:09 +0000 (18:18 +1000)
commitca4eb46aea4cbf835debc94040849c353236179e
treebdf5dc8f81c100cf96f849450748932544e1e673
parentbb5f3563867d66ce2848c5853a6d2b4177d98e69
Make wishbone addresses be in units of doublewords or words

This makes the 64-bit wishbone buses have the address expressed in
units of doublewords (64 bits), and similarly for the 32-bit buses the
address is in units of words (32 bits).  This is to comply with the
wishbone spec.  Previously the addresses on the wishbone buses were in
units of bytes regardless of the bus data width, which is not correct
and caused problems with interfacing with externally-generated logic.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
21 files changed:
dcache.vhdl
dram_tb.vhdl
fpga/top-arty.vhdl
fpga/top-nexys-video.vhdl
gpio.vhdl
icache.vhdl
litedram/extras/litedram-wrapper-l2.vhdl
litedram/gen-src/dram-init-mem.vhdl
litedram/generated/acorn-cle-215/litedram-initmem.vhdl
litedram/generated/arty/litedram-initmem.vhdl
litedram/generated/genesys2/litedram-initmem.vhdl
litedram/generated/nexys-video/litedram-initmem.vhdl
litedram/generated/sim/litedram-initmem.vhdl
soc.vhdl
spi_flash_ctrl.vhdl
syscon.vhdl
wishbone_bram_tb.vhdl
wishbone_bram_wrapper.vhdl
wishbone_debug_master.vhdl
wishbone_types.vhdl
xics.vhdl