xilinx: gate specify/attributes from iverilog
authorEddie Hung <eddie@fpgeh.com>
Wed, 22 Apr 2020 03:44:11 +0000 (20:44 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 14 May 2020 17:33:57 +0000 (10:33 -0700)
commitca4f8c94441c16392ffc02a6117f9b3883e7042e
treeb7af1fa8e8c132f47683ad089690e7d92540e951
parent57c478c537ef23c05ca34ecdf4c4334fd82c104e
xilinx: gate specify/attributes from iverilog
techlibs/xilinx/cells_sim.v