hdl.ir: correctly handle named output and inout ports.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)
commitca6e768dd8cd3799442bf027f215c139a01c764a
tree57e1a6979371660998ba3a38c0f4dbae7ebd0887
parent3d26ed0bdccd989be888832b6b9f827dceca6c56
hdl.ir: correctly handle named output and inout ports.
nmigen/hdl/ir.py
nmigen/test/test_hdl_ir.py