re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)
PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.
testsuite/ChangeLog:
PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.
From-SVN: r255949