re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find...
authorUros Bizjak <uros@gcc.gnu.org>
Thu, 21 Dec 2017 19:00:28 +0000 (20:00 +0100)
committerUros Bizjak <uros@gcc.gnu.org>
Thu, 21 Dec 2017 19:00:28 +0000 (20:00 +0100)
commitcb4b152d88b9c77f552345917601d401010dc4b3
treeb50c571c96b42119ec68231cc9711e0a520dcfc9
parent056cf43428e87bff0703ab4a6ec3558a90328be4
re PR target/83467 (ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv)

PR target/83467
* config/i386/i386.md (*ashl<mode>3_mask): Add operand
constraints to operand 2.
(*ashl<mode>3_mask_1): Ditto.
(*<shift_insn><mode>3_mask): Ditto.
(*<shift_insn><mode>3_mask_1): Ditto.
(*<rotate_insn><mode>3_mask): Ditto.
(*<rotate_insn><mode>3_mask_1): Ditto.

testsuite/ChangeLog:

PR target/83467
* gcc.target/i386/pr83467-1.c: New test.
* gcc.target/i386/pr83467-2.c: Ditto.

From-SVN: r255949
gcc/ChangeLog
gcc/config/i386/i386.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/pr83467-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/pr83467-2.c [new file with mode: 0644]