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(parent: 1fc2e63) | patch
swap RC and RA in divrem2du
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:42:48 +0000 (10:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 29 Apr 2022 09:42:48 +0000 (10:42 +0100)
commitcb775d1230fd46a1f8df256c91af448d7618bacd
treeac10707972b506e26318a8975abcf0579e35f30etree
parent1fc2e63a01c76ac605b43767dfef708a70b6f808commit | diff
swap RC and RA in divrem2du
(oh and do some whitespace, not supposed to combine these, whoops)
openpower/sv/biginteger/analysis.mdwn diff | blob | history
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