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(parent: c5b204d) | patch
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K...
authordh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:04:17 +0000 (11:04 -0500)
committerdh73 <dh73_fpga@qq.com>
Sun, 1 Oct 2017 16:04:17 +0000 (11:04 -0500)
commitcbaba62401ca975bc9aee91b53e0b48fa59bd6c3
treecef8519094b97b32e1412647abbd3a09ab0574a2tree
parentc5b204d8d283d16e6eae8658034da6d378b6810ecommit | diff
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
35 files changed:
backends/verilog/verilog_backend.cc diff | blob | history
techlibs/achronix/Makefile.inc [new file with mode: 0755] blob
techlibs/achronix/speedster22i/cells_arith_speedster.v [new file with mode: 0755] blob
techlibs/achronix/speedster22i/cells_comb_speedster.v [new file with mode: 0755] blob
techlibs/achronix/speedster22i/cells_map_speedster.v [new file with mode: 0755] blob
techlibs/achronix/synth_speedster.cc [new file with mode: 0755] blob
techlibs/altera_intel/Makefile.inc [deleted file] blob | history
techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v [deleted file] blob | history
techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v [deleted file] blob | history
techlibs/altera_intel/lpm_functions.v [deleted file] blob | history
techlibs/altera_intel/max10/cells_arith_max10.v [deleted file] blob | history
techlibs/altera_intel/max10/cells_comb_max10.v [deleted file] blob | history
techlibs/altera_intel/max10/cells_map_max10.v [deleted file] blob | history
techlibs/altera_intel/synth_intel.cc [deleted file] blob | history
techlibs/intel/Makefile.inc [new file with mode: 0755] blob
techlibs/intel/a10gx/cells_arith.v [new file with mode: 0755] blob
techlibs/intel/a10gx/cells_map.v [new file with mode: 0755] blob
techlibs/intel/a10gx/cells_sim.v [new file with mode: 0755] blob
techlibs/intel/common/altpll_bb.v [new file with mode: 0644] blob
techlibs/intel/common/brams.txt [new file with mode: 0755] blob
techlibs/intel/common/brams_map.v [new file with mode: 0755] blob
techlibs/intel/common/m9k_bb.v [new file with mode: 0755] blob
techlibs/intel/cycloneiv/cells_arith.v [new file with mode: 0755] blob
techlibs/intel/cycloneiv/cells_map.v [new file with mode: 0755] blob
techlibs/intel/cycloneiv/cells_sim.v [new file with mode: 0755] blob
techlibs/intel/cycloneive/arith_map.v [new file with mode: 0755] blob
techlibs/intel/cycloneive/cells_map.v [new file with mode: 0755] blob
techlibs/intel/cycloneive/cells_sim.v [new file with mode: 0755] blob
techlibs/intel/cyclonev/cells_arith.v [new file with mode: 0755] blob
techlibs/intel/cyclonev/cells_map.v [new file with mode: 0755] blob
techlibs/intel/cyclonev/cells_sim.v [new file with mode: 0755] blob
techlibs/intel/max10/cells_arith.v [new file with mode: 0755] blob
techlibs/intel/max10/cells_map.v [new file with mode: 0755] blob
techlibs/intel/max10/cells_sim.v [new file with mode: 0755] blob
techlibs/intel/synth_intel.cc [new file with mode: 0755] blob