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(parent: 3eda300) | patch

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 1 Aug 2021 17:37:45 +0000 (18:37 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 1 Aug 2021 17:37:45 +0000 (18:37 +0100)
commit	cbedd169c2d0848fb5bedb076ae401946067ec91
tree	8c3405b912bd1d4d6d45232d736ceb75dd9429b0	tree
parent	3eda30025019034a2e4cf309de818171aa9e4267	commit \| diff

bit of a big update, remove all bit-reversed LD operations, replace with
LD-with-shift, and fix LDST, DCT and FFT unit tests to use new
bitrev-with-half-swap REMAP modes

14 files changed:

openpower/isa/simplev.mdwn		diff \| blob \| history
openpower/isa/svfixedload.mdwn		diff \| blob \| history
openpower/isa/svfpload.mdwn		diff \| blob \| history
src/openpower/consts.py		diff \| blob \| history
src/openpower/decoder/isa/caller.py		diff \| blob \| history
src/openpower/decoder/isa/remap_dct_yield.py		diff \| blob \| history
src/openpower/decoder/isa/svshape.py		diff \| blob \| history
src/openpower/decoder/isa/test_caller_svp64_dct.py		diff \| blob \| history
src/openpower/decoder/isa/test_caller_svp64_fft.py		diff \| blob \| history
src/openpower/decoder/isa/test_caller_svp64_ldst.py		diff \| blob \| history
src/openpower/decoder/power_decoder2.py		diff \| blob \| history
src/openpower/decoder/power_enums.py		diff \| blob \| history
src/openpower/decoder/power_svp64_rm.py		diff \| blob \| history
src/openpower/sv/trans/svp64.py		diff \| blob \| history