Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
authorClifford Wolf <clifford@clifford.at>
Fri, 24 May 2013 13:15:59 +0000 (15:15 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 24 May 2013 13:15:59 +0000 (15:15 +0200)
commitcc0540412832859d28e5c24c8be95c725c10ed19
treea62cdb3cd5c42ef455196dc1925ec9bb6406081f
parent66bc46b30b13ce6f9005edff7a479e28f223a678
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
tests/asicworld/code_verilog_tutorial_fsm_full_tb.v