Renamed RTLIL::{Module,Cell}::connections to connections_
authorClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 09:58:03 +0000 (11:58 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 26 Jul 2014 09:58:03 +0000 (11:58 +0200)
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b
parent665759fceee4a0db3e776b7912e976eea2ff29a3
Renamed RTLIL::{Module,Cell}::connections to connections_
62 files changed:
backends/blif/blif.cc
backends/btor/btor.cc
backends/edif/edif.cc
backends/ilang/ilang_backend.cc
backends/intersynth/intersynth.cc
backends/spice/spice.cc
backends/verilog/verilog_backend.cc
frontends/ast/genrtlil.cc
frontends/ilang/parser.y
frontends/liberty/liberty.cc
kernel/consteval.h
kernel/modwalker.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.h
kernel/sigtools.h
manual/CHAPTER_Prog/stubnets.cc
passes/abc/abc.cc
passes/abc/blifparse.cc
passes/cmds/add.cc
passes/cmds/connect.cc
passes/cmds/connwrappers.cc
passes/cmds/scatter.cc
passes/cmds/scc.cc
passes/cmds/select.cc
passes/cmds/setundef.cc
passes/cmds/show.cc
passes/cmds/splice.cc
passes/cmds/splitnets.cc
passes/fsm/fsm_detect.cc
passes/fsm/fsm_expand.cc
passes/fsm/fsm_extract.cc
passes/fsm/fsm_map.cc
passes/fsm/fsm_opt.cc
passes/fsm/fsmdata.h
passes/hierarchy/hierarchy.cc
passes/hierarchy/submod.cc
passes/memory/memory_collect.cc
passes/memory/memory_dff.cc
passes/memory/memory_map.cc
passes/memory/memory_share.cc
passes/memory/memory_unpack.cc
passes/opt/opt_clean.cc
passes/opt/opt_const.cc
passes/opt/opt_muxtree.cc
passes/opt/opt_reduce.cc
passes/opt/opt_rmdff.cc
passes/opt/opt_share.cc
passes/proc/proc_arst.cc
passes/proc/proc_dff.cc
passes/proc/proc_mux.cc
passes/sat/expose.cc
passes/sat/freduce.cc
passes/sat/miter.cc
passes/sat/sat.cc
passes/sat/share.cc
passes/techmap/dfflibmap.cc
passes/techmap/extract.cc
passes/techmap/hilomap.cc
passes/techmap/iopadmap.cc
passes/techmap/simplemap.cc
passes/techmap/techmap.cc