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(parent: 9e07a75) | patch
arm: Change TLB Software Caching
authorMitch Hayenga <mitch.hayenga@arm.com>
Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)
committerMitch Hayenga <mitch.hayenga@arm.com>
Wed, 30 Sep 2015 16:14:19 +0000 (11:14 -0500)
commitccf4f6c3d7616c546d78eb21d22ebda812b5e2bb
tree08581c6baa40737335733f39d4bab87611ddcceetree
parent9e07a7504c94973e7837d1d3e96dbdb8d95cfad3commit | diff
arm: Change TLB Software Caching

In ARM, certain variables are only updated when a necessary change is
detected.  Having 2 SMT threads share a TLB resulted in these not being
updated as required.  This patch adds a thread context identifer to
assist in the invalidation of these variables.
src/arch/arm/tlb.cc diff | blob | history
src/arch/arm/tlb.hh diff | blob | history