Verilog generator
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 4 Dec 2011 21:26:32 +0000 (22:26 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sun, 4 Dec 2011 21:26:32 +0000 (22:26 +0100)
commitcd8544c7581d8df8f513ef4b920e79a4ef3ba8be
treeafd666bd351e004a69489b04206d06d3f7ed7479
parent499b95a519e6f8015871be74cbc19bef0d75c4f2
Verilog generator
migen/fhdl/structure.py
migen/fhdl/verilog.py [new file with mode: 0644]
test.py