projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 40c3555) | patch
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi
authorGabriel Somlo <gsomlo@gmail.com>
Fri, 29 Nov 2019 23:42:54 +0000 (18:42 -0500)
committerGabriel Somlo <gsomlo@gmail.com>
Sat, 21 Dec 2019 19:11:48 +0000 (14:11 -0500)
commitcd8feca57438ecbcd4e067cc5da3341994119784
tree2b306f3821aba4890cca40f20a0472061a1e78adtree
parent40c355502b453210faef91bbcbde2721345947b3commit | diff
cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi

Various development boards' LiteDRAM ports may have native data
widths of either 64 (nexys4ddr), 128 (versa5g), or 256 (trellis)
bits. Add Rocket variants configured with mem_axi ports of matching
data widths, so that a point to point connection between the CPU's
memory port and LiteDRAM can be accomplished without any additional
data width conversion gateware.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
litex/soc/cores/cpu/__init__.py diff | blob | history
litex/soc/cores/cpu/rocket/core.py diff | blob | history
litex/soc/cores/cpu/rocket/verilog diff | blob | history
litex/soc/integration/soc_sdram.py diff | blob | history