re PR target/62120 ([ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be...

re PR target/62120 ([ICE] ADDITIONAL_REGISTER_NAMES for [YZ]MMs, regno>8 should be disable in 32-bit)

Fix PR 62120.

gcc/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * varasm.c (decode_reg_name_and_count): Check availability for
       registers from ADDITIONAL_REGISTER_NAMES.

testsuite/
2014-09-30  Ilya Tocar  <ilya.tocar@intel.com>

       PR middle-end/62120
       * gcc.target/i386/avx512f-additional-reg-names.c: Use register valid
       in 32-bit mode.
       * gcc.target/i386/pr62120.c: New.

From-SVN: r215729