Renamed port access function on RTLIL::Cell, added param access functions
authorClifford Wolf <clifford@clifford.at>
Thu, 31 Jul 2014 14:38:54 +0000 (16:38 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 31 Jul 2014 14:38:54 +0000 (16:38 +0200)
commitcdae8abe16847c533171fed111beea7b52202cce
treebf8dddb4a4ca4d70c83603ef61b2d22cb95d153a
parentb5a9e51b966abdfedc9309defa79b5141928e84a
Renamed port access function on RTLIL::Cell, added param access functions
46 files changed:
backends/blif/blif.cc
backends/btor/btor.cc
backends/spice/spice.cc
backends/verilog/verilog_backend.cc
frontends/ast/genrtlil.cc
frontends/ilang/parser.y
frontends/liberty/liberty.cc
kernel/consteval.h
kernel/rtlil.cc
kernel/rtlil.h
kernel/satgen.h
passes/abc/abc.cc
passes/abc/blifparse.cc
passes/cmds/add.cc
passes/cmds/connect.cc
passes/cmds/splice.cc
passes/fsm/fsm_detect.cc
passes/fsm/fsm_expand.cc
passes/fsm/fsm_extract.cc
passes/fsm/fsm_map.cc
passes/fsm/fsm_opt.cc
passes/fsm/fsmdata.h
passes/hierarchy/submod.cc
passes/memory/memory_collect.cc
passes/memory/memory_dff.cc
passes/memory/memory_map.cc
passes/memory/memory_share.cc
passes/memory/memory_unpack.cc
passes/opt/opt_const.cc
passes/opt/opt_muxtree.cc
passes/opt/opt_reduce.cc
passes/opt/opt_rmdff.cc
passes/opt/opt_share.cc
passes/proc/proc_arst.cc
passes/proc/proc_dff.cc
passes/proc/proc_mux.cc
passes/sat/expose.cc
passes/sat/freduce.cc
passes/sat/miter.cc
passes/sat/share.cc
passes/techmap/dfflibmap.cc
passes/techmap/extract.cc
passes/techmap/hilomap.cc
passes/techmap/iopadmap.cc
passes/techmap/simplemap.cc
passes/tests/test_cell.cc