mem: Minimize the use of MemObject.
authorGabe Black <gabeblack@google.com>
Tue, 23 Apr 2019 02:45:10 +0000 (19:45 -0700)
committerGabe Black <gabeblack@google.com>
Sun, 28 Apr 2019 01:19:40 +0000 (01:19 +0000)
commitcdcc55a6a8fe9b4625b316a8d8845366ccfa71c9
tree893cea35432466600b55a2e4434ed61ba1e28f69
parent3cfff8574a19536e2b3d057b43b59fcf35932c81
mem: Minimize the use of MemObject.

MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.

Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
105 files changed:
src/arch/arm/ArmTLB.py
src/arch/arm/table_walker.cc
src/arch/arm/table_walker.hh
src/arch/generic/BaseTLB.py
src/arch/generic/tlb.hh
src/arch/x86/X86TLB.py
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/cpu/BaseCPU.py
src/cpu/base.cc
src/cpu/base.hh
src/cpu/o3/checker.cc
src/cpu/o3/cpu.hh
src/cpu/simple/base.cc
src/cpu/testers/directedtest/RubyDirectedTester.cc
src/cpu/testers/directedtest/RubyDirectedTester.hh
src/cpu/testers/directedtest/RubyDirectedTester.py
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
src/cpu/testers/memtest/MemTest.py
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/memtest/memtest.hh
src/cpu/testers/rubytest/RubyTester.cc
src/cpu/testers/rubytest/RubyTester.hh
src/cpu/testers/rubytest/RubyTester.py
src/cpu/testers/traffic_gen/BaseTrafficGen.py
src/cpu/testers/traffic_gen/base.cc
src/cpu/testers/traffic_gen/base.hh
src/cpu/thread_state.hh
src/dev/Device.py
src/dev/dma_device.cc
src/dev/dma_device.hh
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/x86/intdev.hh
src/doc/memory_system.doxygen
src/gpu-compute/GPU.py
src/gpu-compute/LdsState.py
src/gpu-compute/X86GPUTLB.py
src/gpu-compute/compute_unit.cc
src/gpu-compute/compute_unit.hh
src/gpu-compute/gpu_tlb.cc
src/gpu-compute/gpu_tlb.hh
src/gpu-compute/lds_state.cc
src/gpu-compute/lds_state.hh
src/gpu-compute/tlb_coalescer.cc
src/gpu-compute/tlb_coalescer.hh
src/mem/AbstractMemory.py
src/mem/AddrMapper.py
src/mem/Bridge.py
src/mem/CommMonitor.py
src/mem/ExternalMaster.py
src/mem/ExternalSlave.py
src/mem/MemChecker.py
src/mem/MemDelay.py
src/mem/SerialLink.py
src/mem/XBar.py
src/mem/abstract_mem.cc
src/mem/abstract_mem.hh
src/mem/addr_mapper.cc
src/mem/addr_mapper.hh
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/cache/Cache.py
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/comm_monitor.cc
src/mem/comm_monitor.hh
src/mem/dram_ctrl.cc
src/mem/dramsim2.cc
src/mem/external_master.cc
src/mem/external_master.hh
src/mem/external_slave.cc
src/mem/external_slave.hh
src/mem/mem_checker_monitor.cc
src/mem/mem_checker_monitor.hh
src/mem/mem_delay.cc
src/mem/mem_delay.hh
src/mem/mport.hh
src/mem/packet.hh
src/mem/port.cc
src/mem/port.hh
src/mem/qos/mem_sink.cc
src/mem/qport.hh
src/mem/ruby/network/dummy_port.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/ruby/slicc_interface/Controller.py
src/mem/ruby/system/RubyPort.cc
src/mem/ruby/system/RubyPort.hh
src/mem/ruby/system/Sequencer.py
src/mem/ruby/system/WeightedLRUReplacementPolicy.py
src/mem/serial_link.cc
src/mem/serial_link.hh
src/mem/simple_mem.cc
src/mem/tport.cc
src/mem/tport.hh
src/mem/xbar.cc
src/mem/xbar.hh
src/python/m5/SimObject.py
src/sim/System.py
src/sim/cxx_manager.cc
src/sim/system.cc
src/sim/system.hh