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(parent: 3ef88ff) | patch
Added support for parsing attributes on parameters in Verilog frontent. Content of...
authorMaciej Kurc <mkurc@antmicro.com>
Thu, 16 May 2019 10:44:16 +0000 (12:44 +0200)
committerMaciej Kurc <mkurc@antmicro.com>
Thu, 16 May 2019 10:44:16 +0000 (12:44 +0200)
commitce4a0954bc896eedfc2d87e2c9d2b40f42a101db
treeb5bc8a5bbbfd930a9b3a73f862032f1b84935c6ctree
parent3ef88ffbb2409450d5921938b2b938c4c007e091commit | diff
Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
frontends/verilog/verilog_parser.y diff | blob | history