git.libre-soc.org Git - binutils-gdb.git/commit

author	Andrew Cagney <cagney@redhat.com>
	Mon, 25 May 1998 05:48:34 +0000 (05:48 +0000)
committer	Andrew Cagney <cagney@redhat.com>
	Mon, 25 May 1998 05:48:34 +0000 (05:48 +0000)
commit	ce823781894cd9a9a61f7a446b40833f40bb01d3
tree	6e419b97ccd9c2a3a54b1f710b49c62eab3034c4	tree
parent	21b3bc779ca64a3b1d39886a74f0304c8dc96368	commit \| diff

Fix mips SWL on 64bit ISA when 32 bit word appears in second half of
64 bit bus.
Test.

sim/mips/ChangeLog		diff \| blob \| history
sim/testsuite/mips64r5900-elf/t-ldl.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-ldr.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-lwl.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-lwr.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-sdr.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-swl.s	[new file with mode: 0644]	blob
sim/testsuite/mips64r5900-elf/t-swr.s	[new file with mode: 0644]	blob