cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
authorGabe Black <gabeblack@google.com>
Sat, 13 Oct 2018 07:54:32 +0000 (00:54 -0700)
committerGabe Black <gabeblack@google.com>
Wed, 16 Jan 2019 20:27:47 +0000 (20:27 +0000)
commitcf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e
tree75505d60b69951ec0a99ca82e8621803c95d921d
parent0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1
cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
26 files changed:
src/arch/hsail/gpu_isa.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.hh
src/cpu/checker/thread_context.hh
src/cpu/exec_context.hh
src/cpu/kvm/x86_cpu.cc
src/cpu/minor/exec_context.hh
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/dyn_inst.hh
src/cpu/o3/regfile.hh
src/cpu/o3/thread_context.hh
src/cpu/o3/thread_context_impl.hh
src/cpu/simple/exec_context.hh
src/cpu/simple_thread.hh
src/cpu/thread_context.cc
src/cpu/thread_context.hh
src/dev/arm/generic_timer.cc
src/dev/arm/generic_timer.hh
src/gpu-compute/gpu_exec_context.cc
src/gpu-compute/gpu_exec_context.hh
src/gpu-compute/gpu_tlb.cc
src/sim/process.cc
src/sim/process.hh
src/sim/syscall_desc.cc
src/sim/syscall_emul.hh