git.libre-soc.org Git - gem5.git/commit

author	Shivani Parekh <shparekh@ucdavis.edu>
	Thu, 6 Aug 2020 00:35:08 +0000 (17:35 -0700)
committer	Shivani Parekh <shparekh@ucdavis.edu>
	Wed, 26 Aug 2020 16:48:13 +0000 (16:48 +0000)
commit	cf43bc3c8b0c66b713ea8715703102983907fa37
tree	07e8f8845d4ff70fb6b3092c1d8641cc186e8adb	tree
parent	6333e914d3dcd9161a8966abccd8cd8159062131	commit \| diff

mem: Update port terminology

Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

41 files changed:

src/mem/AddrMapper.py		diff \| blob \| history
src/mem/Bridge.py		diff \| blob \| history
src/mem/CommMonitor.py		diff \| blob \| history
src/mem/ExternalMaster.py		diff \| blob \| history
src/mem/MemChecker.py		diff \| blob \| history
src/mem/MemDelay.py		diff \| blob \| history
src/mem/SerialLink.py		diff \| blob \| history
src/mem/XBar.py		diff \| blob \| history
src/mem/addr_mapper.hh		diff \| blob \| history
src/mem/bridge.cc		diff \| blob \| history
src/mem/bridge.hh		diff \| blob \| history
src/mem/cache/Cache.py		diff \| blob \| history
src/mem/cache/base.hh		diff \| blob \| history
src/mem/coherent_xbar.cc		diff \| blob \| history
src/mem/coherent_xbar.hh		diff \| blob \| history
src/mem/comm_monitor.hh		diff \| blob \| history
src/mem/external_master.hh		diff \| blob \| history
src/mem/hmc_controller.cc		diff \| blob \| history
src/mem/mem_checker_monitor.hh		diff \| blob \| history
src/mem/mem_delay.cc		diff \| blob \| history
src/mem/mem_delay.hh		diff \| blob \| history
src/mem/noncoherent_xbar.cc		diff \| blob \| history
src/mem/noncoherent_xbar.hh		diff \| blob \| history
src/mem/packet_queue.cc		diff \| blob \| history
src/mem/packet_queue.hh		diff \| blob \| history
src/mem/port_proxy.hh		diff \| blob \| history
src/mem/qos/QoSMemSinkCtrl.py		diff \| blob \| history
src/mem/qport.hh		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.py		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.hh		diff \| blob \| history
src/mem/ruby/slicc_interface/Controller.py		diff \| blob \| history
src/mem/ruby/system/Sequencer.py		diff \| blob \| history
src/mem/serial_link.cc		diff \| blob \| history
src/mem/serial_link.hh		diff \| blob \| history
src/mem/snoop_filter.cc		diff \| blob \| history
src/mem/snoop_filter.hh		diff \| blob \| history
src/mem/token_port.cc		diff \| blob \| history
src/mem/token_port.hh		diff \| blob \| history
src/mem/xbar.cc		diff \| blob \| history
src/mem/xbar.hh		diff \| blob \| history

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