a6xx: Add more CP packets
authorConnor Abbott <cwabbott0@gmail.com>
Mon, 16 Dec 2019 16:17:38 +0000 (17:17 +0100)
committerConnor Abbott <cwabbott0@gmail.com>
Wed, 18 Dec 2019 22:08:55 +0000 (23:08 +0100)
commitcfa1fb895ac5a752772f4d0748c1c2bce0c2e653
treeeeb9ea0a9c07521abebd6fe875f9f2416f1562fb
parenta9a3108be774aea620fa4fc726c33100d9a49add
a6xx: Add more CP packets

And add fields uncovered by looking at the firmware. I think this covers
all the memory, register, and scratch manipulation opcodes that exist on
A6xx, plus one additional nice find for Vulkan and describing a
previously unknown opcode and documenting CP_WAIT_REG_MEM.

Note that the bits for the CP_REG_TO_MEM count, as well as the formula
for computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG,
are changed because the A630 SQE firmware actually does something
different. I haven't investigated older microcodes to see whether this
extends back to A5xx and A4xx, but the only non-A6xx uses of this
field result in the same bit-pattern when using the A6xx bit range and
formula, so it should be safe to change the definition universally.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
src/freedreno/registers/adreno_pm4.xml
src/freedreno/vulkan/tu_cmd_buffer.c
src/gallium/drivers/freedreno/a4xx/fd4_query.c
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
src/gallium/drivers/freedreno/a6xx/fd6_query.c