verilog: fix signedness when removing unreachable cases
authorJannis Harder <me@jix.one>
Tue, 24 May 2022 12:32:14 +0000 (14:32 +0200)
committerZachary Snow <zachary.j.snow@gmail.com>
Wed, 25 May 2022 03:03:31 +0000 (23:03 -0400)
commitcffec1f95f0ac4bad1deb24bf7f921bd93145a16
treec66eeb0e812b0519e8f72791c70e2b6dc44d7df3
parentc525b5f91925bd51194ead99a4ecace313f9945c
verilog: fix signedness when removing unreachable cases
CHANGELOG
frontends/ast/simplify.cc
tests/verilog/unreachable_case_sign.ys [new file with mode: 0644]