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(parent: 6b0c51c) | patch
Make the SR, FSR and FIR registers 32 bits regardless of the target.
authorAndrew Cagney <cagney@redhat.com>
Wed, 1 Apr 1998 14:26:37 +0000 (14:26 +0000)
committerAndrew Cagney <cagney@redhat.com>
Wed, 1 Apr 1998 14:26:37 +0000 (14:26 +0000)
commitd0136bf32ac68edd8d191559e2dea1d0a7ca6555
treeafd83ff9d74740dff11fb9bee0f9c6b5d26797datree
parent6b0c51c9299c47f0ad37e8a32a4963deed6f9580commit | diff
Make the SR, FSR and FIR registers 32 bits regardless of the target.
gdb/ChangeLog diff | blob | history
gdb/config/mips/tm-mips.h diff | blob | history
gdb/config/mips/tm-mips64.h diff | blob | history