projects / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 1666ee1) | patch
radeonsi/gfx10: mask DCC tile swizzle by alignment
authorNicolai Hähnle <nicolai.haehnle@amd.com>
Mon, 23 Jul 2018 07:47:19 +0000 (09:47 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 3 Jul 2019 19:51:13 +0000 (15:51 -0400)
commitd028440f578fb2ab96e64846c8f378bd6b247886
tree89865332704024b48871a54e8935bc4f2435b4betree
parent1666ee183e2dd0ae78cbec236315ad6328692589commit | diff
radeonsi/gfx10: mask DCC tile swizzle by alignment

DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/gallium/drivers/radeonsi/si_descriptors.c diff | blob | history
src/gallium/drivers/radeonsi/si_state.c diff | blob | history