fastmodel: Implement flattened int reg reading and writing.
authorGabe Black <gabeblack@google.com>
Wed, 13 Nov 2019 00:52:05 +0000 (16:52 -0800)
committerGabe Black <gabeblack@google.com>
Thu, 6 Feb 2020 01:07:16 +0000 (01:07 +0000)
commitd062a82f112640436fdb99f21884363557cede9b
treec10f306ba997ef15db0d936270e3a4e46282ba83
parent00d324b8cc3ef8fadf2825315fa2b8b12ee96967
fastmodel: Implement flattened int reg reading and writing.

Because the fast models (or at least the one we've looked at) give
access to the integer registers mostly based on the current view of
those registers, it does its own flattening and prevents accessing most
of the raw storage locations without this extra level of mapping. To
store to the flattened locations, we need to unflatten the indexes and
in one case shift the mode so that we get the right values.

Some registers which have irrelevant values for fast model (the "PC"
which is actually diverted elsewhere, the zero register, microcode
registers, and the "dummy" register), and those are left out of the
mapping so that they return 0 and blow up gem5 when someone attempts to
set them.

Change-Id: Ia2d315d5ca4c8a65b17ad52beff3a366ca8b3d46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23791
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
src/arch/arm/fastmodel/CortexA76/thread_context.cc
src/arch/arm/fastmodel/CortexA76/thread_context.hh
src/arch/arm/fastmodel/iris/thread_context.cc
src/arch/arm/fastmodel/iris/thread_context.hh