git.libre-soc.org Git - binutils-gdb.git/commit

author	Mike Frysinger <vapier@gentoo.org>
	Thu, 24 Jun 2021 03:23:27 +0000 (23:23 -0400)
committer	Mike Frysinger <vapier@gentoo.org>
	Wed, 16 Feb 2022 05:36:47 +0000 (00:36 -0500)
commit	d0b2f561a1e8ef6ecf87a99f220262d58538c750
tree	551de4314e04ce7f888ab2fa58cb34f3912ff482	tree
parent	bc85f56bfda7162688b9bea8dd942ec473bdb21b	commit \| diff

sim: testsuite: cleanup the istarget * logic

Now that the multitarget testing has settled, clean up the cases where
istarget * is used. This ends up being mostly style unindenting.

46 files changed:

sim/testsuite/aarch64/allinsn.exp		diff \| blob \| history
sim/testsuite/arm/allinsn.exp		diff \| blob \| history
sim/testsuite/arm/iwmmxt/iwmmxt.exp		diff \| blob \| history
sim/testsuite/arm/misc.exp		diff \| blob \| history
sim/testsuite/arm/thumb/allthumb.exp		diff \| blob \| history
sim/testsuite/arm/xscale/xscale.exp		diff \| blob \| history
sim/testsuite/avr/allinsn.exp		diff \| blob \| history
sim/testsuite/bfin/allinsn.exp		diff \| blob \| history
sim/testsuite/bpf/allinsn.exp		diff \| blob \| history
sim/testsuite/cr16/allinsn.exp		diff \| blob \| history
sim/testsuite/cr16/misc.exp		diff \| blob \| history
sim/testsuite/cris/asm/asm.exp		diff \| blob \| history
sim/testsuite/d10v/allinsn.exp		diff \| blob \| history
sim/testsuite/example-synacor/allinsn.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-a-b.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-c.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-d-h.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-i-l.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-m.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-n.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-o-s.exp		diff \| blob \| history
sim/testsuite/frv/allinsn-t-z.exp		diff \| blob \| history
sim/testsuite/frv/fr400/allinsn.exp		diff \| blob \| history
sim/testsuite/frv/fr500/allinsn.exp		diff \| blob \| history
sim/testsuite/frv/fr550/allinsn.exp		diff \| blob \| history
sim/testsuite/frv/interrupts.exp		diff \| blob \| history
sim/testsuite/frv/misc.exp		diff \| blob \| history
sim/testsuite/frv/parallel.exp		diff \| blob \| history
sim/testsuite/ft32/allinsn.exp		diff \| blob \| history
sim/testsuite/h8300/allinsn.exp		diff \| blob \| history
sim/testsuite/iq2000/allinsn.exp		diff \| blob \| history
sim/testsuite/lm32/allinsn.exp		diff \| blob \| history
sim/testsuite/m32c/allinsn.exp		diff \| blob \| history
sim/testsuite/m32r/allinsn.exp		diff \| blob \| history
sim/testsuite/m32r/misc.exp		diff \| blob \| history
sim/testsuite/m68hc11/allinsn.exp		diff \| blob \| history
sim/testsuite/mcore/allinsn.exp		diff \| blob \| history
sim/testsuite/microblaze/allinsn.exp		diff \| blob \| history
sim/testsuite/mn10300/allinsn.exp		diff \| blob \| history
sim/testsuite/moxie/allinsn.exp		diff \| blob \| history
sim/testsuite/msp430/allinsn.exp		diff \| blob \| history
sim/testsuite/or1k/alltests.exp		diff \| blob \| history
sim/testsuite/pru/allinsn.exp		diff \| blob \| history
sim/testsuite/riscv/allinsn.exp		diff \| blob \| history
sim/testsuite/sh/allinsn.exp		diff \| blob \| history
sim/testsuite/v850/allinsns.exp		diff \| blob \| history

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