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(parent: d3f7cc8) | patch
back.rtlil: don't cache wires for legalized switch tests.
authorwhitequark <whitequark@whitequark.org>
Wed, 2 Oct 2019 07:51:49 +0000 (07:51 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 2 Oct 2019 07:51:49 +0000 (07:51 +0000)
commitd139f340b33ce79dcb97f29b9e08f544a650e52b
tree6ad8d7ba96231a9021fd52cf142675d76c4d3e59tree
parentd3f7cc8ed2a81480b232fe736bde3e786dde9e59commit | diff
back.rtlil: don't cache wires for legalized switch tests.

This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
nmigen/back/rtlil.py diff | blob | history