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(parent: 98bb1c6) | patch
Split CachePort class into CpuSidePort and MemSidePort
authorSteve Reinhardt <stever@eecs.umich.edu>
Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)
committerSteve Reinhardt <stever@eecs.umich.edu>
Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)
commitd172e1576a9d8fd422d881c8f72a9c5cc4b6b9a6
tree93bfd057e44d9c450d0c1103d668de9ec9dda8fctree
parent98bb1c62b31e988f81d9fc03cf14aca25fd008dbcommit | diff
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).

--HG--
extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
src/mem/cache/base_cache.cc diff | blob | history
src/mem/cache/base_cache.hh diff | blob | history
src/mem/cache/cache.hh diff | blob | history
src/mem/cache/cache_impl.hh diff | blob | history