arch-riscv: CSR registers support in RISC-V remote GDB.
authorPeter Yuen <ppeetteerrsx@gmail.com>
Mon, 11 Jan 2021 16:38:23 +0000 (00:38 +0800)
committerPeter Yuen <ppeetteerrsx@gmail.com>
Thu, 14 Jan 2021 03:29:34 +0000 (03:29 +0000)
commitd1933d9ce7aeb9c3da1339e850720dbc30237f58
tree13a977ad5dfca3737d1ab25cff81a87788aa96ac
parent9c7cc711bcb35cd7938bb133382f45bf13d10cbc
arch-riscv: CSR registers support in RISC-V remote GDB.

Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.

Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs

Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38955
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ext/gdb-xml/riscv-64bit-cpu.xml [new file with mode: 0644]
ext/gdb-xml/riscv-64bit-csr.xml [new file with mode: 0644]
ext/gdb-xml/riscv-64bit-fpu.xml [new file with mode: 0644]
ext/gdb-xml/riscv.xml [new file with mode: 0644]
src/arch/riscv/SConscript
src/arch/riscv/remote_gdb.cc
src/arch/riscv/remote_gdb.hh