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(parent: 54f89af) | patch
loadstore1: Improve timing of data path from cache RAM to writeback
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 28 Sep 2020 04:02:03 +0000 (14:02 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Fri, 15 Jan 2021 01:40:09 +0000 (12:40 +1100)
commitd1f35705c07d4468b3943467683ca2501731e41c
treea591823637b3d73f5b4beb99995a803475b00673tree
parent54f89afab7bc2b58dc48759a68cc8c56954a6b6dcommit | diff
loadstore1: Improve timing of data path from cache RAM to writeback

Work out select inputs for writeback mux a cycle earlier.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
loadstore1.vhdl diff | blob | history