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(parent: 01df3a4) | patch
fix up simulation to be more like VERSA_ECP5
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 1 Mar 2022 15:22:20 +0000 (15:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 1 Mar 2022 15:22:20 +0000 (15:22 +0000)
commitd20b197326aabbe769dac42793721ba1c0c4e750
treefbba78d4f8fbc575258a10171862f1d215052a5btree
parent01df3a4b09d11c893a1ee1f658728f9a78d70c30commit | diff
fix up simulation to be more like VERSA_ECP5
* use MT4164M16 instead of MT41256M16
* add a Chip-Select line (dram_cs_n) which is currently inverted
* reduce the number of address lines in the simulated platform
gram/simulation/icarusecpix5platform.py diff | blob | history
gram/simulation/simsoc.py diff | blob | history
gram/simulation/simsoctb.v diff | blob | history