verilog: ignore ranges too without -specify
authorEddie Hung <eddie@fpgeh.com>
Fri, 14 Feb 2020 01:58:43 +0000 (17:58 -0800)
committerEddie Hung <eddie@fpgeh.com>
Fri, 14 Feb 2020 01:58:43 +0000 (17:58 -0800)
commitd20c1dac73e344dda73ec2b526ffb764efc9fdd8
tree77397933b425f31f0684572daa2df01cc39fd182
parent6b58c1820c7bbacb4730af40e10592823b0eb15c
verilog: ignore ranges too without -specify
frontends/verilog/verilog_parser.y
tests/various/specify.v